1. Field of the Invention
The present invention relates to a method and an apparatus for testing semiconductor devices. More particularly, the invention relates to a testing method and a testing apparatus for preventing an inordinate drop in the yield of semiconductor devices having a built-in self-test function.
2. Description of the Related Art
As today""s logic integrated circuits become progressively larger in scale, large quantities of them are fabricated in the form of semiconductor integrated circuit (IC) devices comprising a built-in self-test (BIST) function. This function is designed to test the main circuits of each semiconductor device. Traditionally, well-known automatic test equipment (ATE) such as VLSI testers has been used as standard equipment for subjecting semiconductor devices to GO/NO-GO tests (xe2x80x9cGOxe2x80x9d will stand for compliance with product requirements and xe2x80x9cNO-GOxe2x80x9d for noncompliance hereunder).
When such standard ATE is used to test IC chips having a built-in self-test (BIST) circuit each, it is customary for the equipment to test the BIST circuit of each IC chip before testing its main circuits, i.e., the proper target of testing. Because there is a possibility that the BIST circuit itself can be defective, it is necessary to test the BIST circuit first to confirm whether the BIST circuit itself is defective or not; no results of tests performed with potentially faulty BIST circuits are credible.
FIG. 12 is a flowchart of steps constituting a conventional method for testing IC chips incorporating a built-in self-test function each. In FIG. 12, one of the semiconductor devices included in a wafer is first selected. With built-in self-test mode established, the BIST circuit of the selected device is subjected to a self-diagnostic test. If the result of the self-diagnostic test is GO, then the main circuits of the device are tested by the BIST circuit. If the result of the main circuit test by the BIST circuit is GO, then the main circuits are tested without recourse to the BIST circuit. Illustratively, a memory portion of the main circuits is tested first in a test A. If the result of the test A is GO, then a logic portion of the main circuits is tested in a test B. If the result of the test B is GO, then the IC chip equipped with the built-in self-test function is judged to be normal. If any of the results from the self-diagnostic test of the BIST circuit, the main circuit test by the BIST circuit, the test A or the test B is NO-GO, the semiconductor device in question is rejected as defective at the point of the judgment. The testing of the current IC chip with the BIST circuit is stopped forthwith, and the next semiconductor device is reached for another round of tests.
One disadvantage of the conventional testing method above is that if the BIST circuit itself is faulty, the circuit can inadvertently judge the host IC chip to be defective. In such cases, the main circuits may in fact be normal but are rejected nevertheless.
Unless each BIST circuit is guaranteed 100 percent normal, there can be an inordinate decline in the yield of semiconductor devices containing the self-diagnostic circuitry in produce. For that reason, some manufacturers have eschewed the BIST scheme outright; others still adopt BISTs but with such difficulties that the tests have failed to be fully effective in the mass fabrication of semiconductor devices.
In connection with this invention, Japanese Patent Laid-Open No. 2000-131394 discloses techniques for retrieving data in user mode from desired flip-flops in an internal logic circuit through the use of a boundary scan test control circuit and scan paths for the BIST scheme.
The present invention has been made to overcome the above-described drawbacks and disadvantages, and a first object of the invention is to provide a method for testing semiconductor devices in a way that prevents a defective built-in self test function from falsely judging the host semiconductor device to be flawed.
According to one aspect of the invention, there is provided a semiconductor device testing method applied to a plurality of semiconductor devices on a wafer, each of the semiconductor devices including a main circuit part, a test function part for testing the main circuit part, and a switching circuit part for switching a test signal either to the main circuit part or to the test function part upon receipt of an external signal, the method comprising the steps of: firstly sending a test signal through the switching circuit part of a given semiconductor device to the test function part thereof thereby subjecting the test function part to a self-diagnostic and testing the main circuit part using the test function part for compliance with relevant requirements, judging the semiconductor device in question to be faulty if either the self-diagnostic of the test function part or the test on the main circuit part by the test function part has produced an abnormal result, and the result of the testing being saved; secondly supplying the main circuit part of the semiconductor device judged faulty in the first step with a test signal through the switching circuit part thereby testing the main circuit part for compliance with the requirements; and thirdly judging the semiconductor device to be normal if the main circuit part thereof was judged normal in the second step.
Accordingly, this method eliminates the possibility that any chip with normal main circuits can be rejected as defective if the result of the self-diagnostic of the built-in test function part turns out to be abnormal. The inventive testing method thus circumvents high rates of semiconductor devices getting falsely rejected because of their flawed built-in self-test circuits and thereby improves the yield rates of the devices. That in turn makes it possible to fabricate highly reliable and inexpensive semiconductor devices with the built-in self-test function.
Anther object of the invention is to provide an apparatus for testing semiconductor devices in a way that prevents a defective built-in self-test function from falsely judging the host semiconductor device to be flawed.
According to another aspect of the invention, there is provided a semiconductor device testing apparatus comprising: a drive element that carries a wafer including a plurality of semiconductor devices each having a main circuit part, a test function part for testing the main circuit part, and a switching circuit part for switching a test signal either to the main circuit part or to the test function part upon receipt of an external signal, the drive element further moving the semiconductor device of the wafer to suitable position; a signal transmission element that transmits signals to suitable semiconductor devices on the wafer carried by the drive element; and a central processing element that sends a test signal through the switching circuit part of a semiconductor device suitably positioned by the drive element, to the test function part of the device in question thereby subjecting the test function part to a self-diagnostic and testing the main circuit part using the test function part for compliance with relevant requirements, before judging the semiconductor device in question to be faulty in a first judging step if either the self-diagnostic of the test function part or the test on the main circuit part by the test function part has produced an abnormal result, the result of the testing being saved; the central processing element further moving the drive element up to the position of any semiconductor device judged faulty in the first judging step and supplying the main circuit part of the semiconductor device in question with a test signal through the switching circuit part thereby testing the main circuit part in a second judging step; the central processing element further judging the semiconductor device to be normal if the main circuit part thereof was judged normal in the second judging step.
Accordingly, This inventive testing apparatus does not reject semiconductor devices as defective if the self-diagnostic of their test function part produces an abnormal result while their main circuits are judged normal. The apparatus averts high rates of semiconductor devices getting falsely rejected because of abnormal results of the self-diagnostic on their test function part. That in turn makes it possible to fabricate highly reliable and inexpensive semiconductor devices with the built-in self-test function.
Other objects and advantages of the invention will become apparent from the detailed description given hereinafter. It should be understood, however, that the detailed description and specific embodiments are given by way of illustration only since various changes and modifications within the scope of the invention will become apparent to those skilled in the art from this detailed description.